With continuous development of large-scale integrated circuits, circuit lines become thinner and thinner as the 22 nm circuit line has been widely used in mass production. The thinning requirement of circuit lines brings about an unprecedented challenge to devices and processes. In order to further develop the chip density and the signal processing capability of per unit circuit area, a 3D packaging process was therefore invented. In the 3D packaging process, chips are stacked to form a 3D integrated packaging structure so that the packing density of per unit circuit area can be increased.
With the development of the 3D packaging process, the requirement of an organic substrate becomes more strict, as the circuit line/space of the organic substrate has reduced from 100 μm (PCB level) to 30-50 μm (mass production level), the surface roughness of the copper circuit should become smaller. Normally, the roughness of copper in PCB (Printed Circuit Board) is Rz=5-7 μm while that of substrates is below 5 μm. For copper lines which line/space is 10-20 μm, the roughness is required under 2 μm; Or, a short-circuit fault may be caused due to a circuit deformation or the residual copper between circuit lines and further a high accuracy interconnection structure cannot be achieved.
Moreover, the roughness of copper lines on the organic substrates should meet the requirements of different transmission frequencies of signals. For 10GHz signals, the roughness of copper circuit surface should be no more than 1 μm. For 100GHz signals, the roughness should be less than 0.1 μm.
A conventional process to improve the surface roughness is to etch the surfaces of circuit boards by an oxidant. Since different surface molecules have different reactions to the oxidant, some functional groups are removed to form etching pits. The removed functional groups are not evenly distributed on the surface of circuit boards, so that a rough surface can be achieved due to the uneven distributed etching pits. Conventional etching process may bring a big height difference of the etching pits as ranging from several μm to even a larger scope.
In the prior art, three processes are normally used to produce the organic substrate and PCB: an additive process, subtractive process and semi-additive process. While, due to the high development of IC package technology, the feature size of the package substrate has decreased from 100 μm to 50 μm. Some advanced package substrates have even reached a level of 25-30 μm, and some suppliers are attempting the mass production of circuits with a line width of 15 μm.
As for the circuits with a line/space larger than 50 μm, the subtractive process is normally used, during which a prepreg is applied as an insulation medium and the external circuit structure is constructed by laminating a copper foil onto the prepreg under high temperature.
As for the circuits with a line/space below 50 μm, the subtractive process is entirely not applicable, since it cannot guarantee the size accuracy of circuits. The additive process is barely used since the electroless copper plating is too slow.
The Semi-Additive Process, namely SAP, has become a main process to manufacture organic substrates with high-density circuits and has been widely used in constructing high accuracy circuit structures. During a conventional SAP, the electroless copper plating process is directly implemented on the resin substrate surface. In order to achieve a better adhesion of copper lines on the resin substrate, the resin substrate surface should be coarsened to obtain a certain roughness. However, as there is glass cloth comprised in the normal prepreg, during lamination of the prepreg onto the surface of the inner circuit substrate, the glass cloth may be exposed due to the resin flowing. Or only a very thin resin layer may be left on the surface of glass cloth, after the coarsening process on the resin substrate surface, the very thin resin layer may be etched off, which will also lead to the exposure of glass cloth. In this case, the electroless copper plating process may not be able to be implemented, or the adhesion of the electroless plating copper layer may be low, on some regional surfaces where the glass cloth is exposed.
To solve the problem in SAP, a Modified Semi-Addictive Process, namely MSAP, is used to produce the organic substrate with a line/space below 50 μm. During the MSAP process, a 3 μm ultrathin copper foil is laminated onto the prepreg' s surface and then is reduced to 1-2 μm. A plating pattern is formed through a dry film patterning process; after an electrolytic copper plating process, the dry film is removed and the copper foil under the dry film is corroded off to form circuits. Since the material density of the ultrathin copper foil is much larger than the pattern plating copper, the corroding speeds of them are greatly different. In this case, the pattern plating copper on the whole surface may also be quickly corroded during the corroding process of the ultrathin copper foil. In summary, the final circuit accuracy may be seriously influenced by the mask design in pattern plating, parameters of electroplating, thickness of the ultrathin copper foil and parameters of the flash etching process of the ultrathin copper foil. So, it is difficult to apply MASP on producing the organic substrate with a line/space below 20 μm. Consequently, although the MSAP is able to manage the adhesion of circuits on the substrate, it cannot achieve a high accuracy of the circuit.
Therefore, due to the strict requirements of the insulation ability, adhesion and circuit accuracy, normal materials are not suitable for producing an organic substrate with a line width below 50 μm.
However, the Mitsubishi Company has provided a material named PCF (Primer Coated Copper Foil) which can satisfy the mentioned requirements.
FIG. 1 illustrates the structure of a PCF in the prior art. The PCF is obtained by coating a resin layer 9′ on a low roughness copper foil 8′. The thickness of the resin layer 9′ is around 2-3 μm.
FIG. 2a˜2b and FIG. 3a˜3i illustrate the flow chart of a SAP using a PCF in the prior art. As shown in FIG. 2a˜2b and FIG. 3a˜3i, the process includes following steps.
Step 101: as shown in FIG. 3a and 3b, two prepregs 11′ are respectively laminated on both surfaces of an inner circuit substrate 1′, and then a PCF 10′ is laminated onto each of the prepregs 11′.
Step 102: as shown in FIG. 3c, blind vias 3′ are drilled through the PCF 10′ and the prepreg 11′ by a laser drilling process.
Step 103: blind vias 3′ are swelled and the smear in the blind vias 3′ is removed.
Step 104: as shown in FIG. 3d, the copper foil 8′ is removed from the PCF 10′.
Step 105: all the surface of the resin layer 9′ are swelled.
Step 106: as shown in FIG. 3e, an electroless copper plating process is implemented on the resin layer 9′ and the blind vias 3′ to form an electroless plating copper layer 4′, and the electroless copper plating process includes: acid soaking, cleaning, micro corroding, pre-soaking, activating, reducing and electroless copper plating.
Step 107: as shown in FIG. 3f, a photolithography process is implemented to construct a dry film layer 5′ on the electroless plating copper layer 4′, wherein pattern plating windows 6′ are exposed on proper locations of the dry film layer 5′ including positions corresponding to blind vias 3′ for following electroplating.
Step 108: as shown in FIG. 3f, an electroplating plating process is implemented on the pattern plating windows 6′ to form a copper plating pattern 7′.
Step 109: as shown in FIG. 3h, the dry film 5′ is removed by using stripping liquid to form a substrate with the copper plating pattern 7′.
Step 110: as shown in FIG. 3i, the whole substrate is dipped in etchant to corrode off the remained electroless plating copper layer 4′. Since the electroless plating copper layer 4′ is very thin and its corroding speed is very rapid, an external circuit structure is formed after the electroless plating copper layer 4′ is corroded off.
More external circuit structures can be further constructed by repeating the Steps 101˜110.
In the SAP using a PCF, the surface roughness of the copper foil is transferred to the resin layer. After the copper foil is removed, the electroless copper plating process and the subsequent electroplating plating process are directly implemented on the resin layer. The resin layer of the PCF which is a patented product belonging to Mitsubishi Company is made of special materials. The electroless copper plating process can be directly implemented on the resin layer to achieve an excellent adhesion.
In a SAP using the PCF in the prior art, the swelling process is implemented in the blind vias and the resin layer.
Moreover, the Ajinomoto Company has produced a material named ABF (Ajinomoto Build-up Film). The ABF is a kind of prepreg material without glass cloth. By using the ABF as the insulation layer, an excellent external layer circuit structure can be achieved through the SAP. Therefore it has been widely used in the manufacture of advanced circuit substrates. The resin material of the ABF is obtained by adding micro glass powder into epoxy. After a lamination process, a rough resin surface is achieved by forming etching pits on the surface of the resin material after etching off the micro glass powder. Currently, the diameter of the monox powder in GX-13 epoxy resin, a featured product of the Ajinomoto Company, is below 5 μm and GX-13 is used in the SAP to construct a circuit structure with a line width below 15 μm. Subsequent products with even smaller micro glass powder may be produced, actually, produces with micro glass powder which diameter is smaller than 1 μm have also been produced.
FIG. 4a˜4b and FIG. 5a˜5h illustrate the flow chart of a SAP using an ABF. As shown in FIG. 4a˜4b and FIG. 5a˜5h, the process includes following steps.
Step 201: as shown in FIG. 5a, an inner circuit substrate 1′ is manufactured. Step 202: as shown in FIG. 5b, ABFs 2′ are respectively laminated on both surfaces of the inner circuit substrate 1′.
Step 203: as shown in FIG. 5c, blind vias 3′ are drilled on the ABF 2′ through a laser drilling process.
Step 204: as shown in FIG. 5d, an electroless copper plating process is implemented on the ABF to form an electroless plating copper layer 4′; the electroless copper plating process includes: swelling, desmearing, neutralizing, acid soaking, cleaning, micro corroding, pre-soaking, activating, reducing and electroless copper plating.
Step 205: as shown in FIG. 5e, a photolithography process is implemented to construct a dry film layer 5′ on the electroless plating copper layer 4′. Pattern plating windows 6′ are exposed on proper locations of the dry film layer 5′ including positions corresponding to blind vias 3′ for following electroplating.
Step 206: as shown in FIG. 5f, an electroplating process is implemented on the pattern plating windows 6′ to form a copper plating pattern 7′.
Step 207: as shown in FIG. 5g, the dry film 5′ is removed by using stripping liquid to form a substrate with the copper plating pattern 7′.
Step 208: as shown in FIG. 5h, the whole circuit board is dipped in etchant to corrode off the remained electroless plating copper layer 4′. Since the electroless plating copper layer 4′ is very thin and its corroding speed is very rapid, an external circuit structure is formed after the electroless plating copper layer 4′ is corroded off
In a SAP using the ABF in the prior art, a desmearing process is required after the swelling process to remove the monox powder, and the swelling process improves roughening of the resin surface.
Moreover, the price of the PCF is much higher than the prepreg, the SAP using the PCF costs twice as much as the cost of conventional subtractive manufacture processes which only using one layer of the prepreg. The ABF is 4-5 times expensive than the prepreg due to its costs and its patent fee, and it is twice as expensive as the cost of the combination of the PCF and prepreg. Hence, the cost of SAP using either the ABF or the PCF is pretty high.